Recent Publications

Selected publications are available in Adobe Acrobat format
  1. Valery Axelrad, "Design and Simulation of ESD-Resistant ICs", MIXDES 2013 , Gdynia, Poland

  2. Michael C. Smayling, Koichiro Tsujita, Hidetami Yaegashi, Valery Axelrad, Tadashi Arai, Kenichi Oyama, Arisa Hara, "Sub-12nm Optical Lithography with 4x Pitch Division and SMO-LiteTM", Proceedings of SPIE In Microlithography 2013, San Jose

  3. Michael C. Smayling, Valery Axelrad, Koichiro Tsujita, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, Yuichi Gyoda, "Sub-20nm Logic Lithography Optimization with Simple OPC and Multiple Pitch Division", Proceedings of SPIE In Microlithography 2012, San Jose

  4. Koichiro Tsujita, Koji Mikami, Tadashi Arai, Ryo Nakayama, Michael C. Smayling, Valery Axerad, Hidetami Yaegashi, Kenichi Oyama, "Improvement of lithographic performance and reduction of mask cost", Photomask Technology BACUS 2012, Monterey, Sept. 2012

  5. Valery Axelrad, Koichiro Tsujita, Koji Mikami, Ryo Nakayama, "Resist Diffusion Model for Fast and Accurate sub-20nm Lithography Simulation", SISPAD 2012, Denver, Sept. 2012

  6. V. Axelrad, H. Hayashi*, I. Kurachi, "Physical Circuit-Device Simulation of ESD and Power Devices," SISPAD 2011, Osaka, Japan, Sept. 2011

  7. Koichiro Tsujita, Tadashi Arai, Hiroyuki Ishii, Yuichi Gyoda, Kazuhiro Takahashi, Valery Axelrad, Michael C. Smayling, "Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization," Proc. SPIE 7973, Proceedings of SPIE In Microlithography 2011, San Jose

  8. V. Axelrad, M. C. Smayling, K. Tsujita, K. Takahashi, "Optical lithography applied to 20nm CMOS Logic and SRAM," Proc. SPIE 7973-39, Proceedings of SPIE In Microlithography 2011, San Jose

  9. V. Axelrad, M. C. Smayling, "16nm with 193nm Immersion Lithography and Double Exposure," Proc. SPIE 7641 (2010), Proceedings of SPIE In Microlithography 2010, San Jose

  10. Michael C. Smayling, Valery Axelrad, "32nm and below Logic Patterning using Optimized Illumination and Double Patterning", SPIE Microlithography, Feb. 2009

  11. Koichiro Tsujita, Koji Mikami, Hiroyuki Ishii, Ryo Nakayama, Mikio Arakawa, Takehiro Ueno, Shogo Fujie, and Kazuhiro Takahashi , "Innovative pattern matching method considering process margin and scanner design information", SPIE Microlithography, Feb. 2009

  12. Smayling, M.C., Axelrad, V. "Simulation-Based Lithography Optimization for Logic Circuits at 22nm and Below", SISPAD 2009, San Diego, 2009
  13. Michael C. Smayling, Valery Axelrad, Michael P. Duane, James Yu1, Hui W. Chen, "Cell-Based Aerial Image Analysis of Design Style for 45nm Generation Logic", SPIE Microlithography, Feb. 2007
    PowerPoint Slides
  14. Oleg Semenov, Arman Vassighi and Manoj Sachdev, "Impact of Self-Heating Effect on Long-Term Reliability and Performance Degradation in CMOS Circuits", IEEE Transactions On Device And Materials Reliability, Vol. 6, No. 1, March 2006
  15. V. Axelrad, A. Shibkov, H. Hayashi, K. Fukuda, "Implementation of ESD Protection in SOI Technology: A Simulation Study", 2005 International Conferenceon Simulation of Semiconductor Processes and Devices (SISPAD 2005), Sept.2005, Tokyo, Japan
  16. Hirokazu Hayashi, Toshikazu Kuroda, Katsuhiro Kato, Koichi Fukuda, Shunsuke Baba, and Yasuhiro Fukuda, "ESD Protection Design Optimization Using a Mixed-Mode Simulationand Its Impact on ESD Protection Design of Power Bus Line Resistance", 2005 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2005), Sept. 2005, Tokyo, Japan
  17. A. Shibkov, V. Axelrad, "Integrated Simulation Flow for Self-Consistent Manufacturability and Circuit Performance Evaluation", 2005 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2005), Sept. 2005, Tokyo, Japan
  18. Valery Axelrad, Andrei Shibkov, Gene Hill, Hung-Jen Lin, Cyrus Tabery, Dan White, Victor Boksha, Randy Thilmany, "A Novel Design-Process Optimization Technique Based on Self-Consistent Electrical Performance Evaluation", SPIE Microlithography 2005, Santa Clara, USA
  19. Hirokazu Hayashi, Toshikazu Kuroda, Katsuhiro Kato, Koichi Fukuda, Shunsuke Baba, and Yasuhiro Fukuda "ESD Protection Design Using a Mixed-Mode Simulation for Advanced Devices" 2004 EOS/ESD Symposium
  20. V. Axelrad, A. Shibkov, "Analysis and Optimization of ESD Protection Circuits with Feedback Triggering", International Conference on Solid State Devices and Materials (SSDM 2004) September 14-17 2004, Tokyo, Japan
  21. V. Axelrad, A. Balasinski, W. Baker, A. Shibkov, "Efficient Analysis and Optimization of ESD Protection Circuits",  International Conference on Solid State Devices and Materials (SSDM 2004) September 14-17 2004, Tokyo, Japan
  22. O. Semenov, H. Sarbishaei, V. Axelrad and M. Sachdev, "The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness", Microelectronics Reliability 44 (2004) 1817-1822.
  23. H. Hayashi, K. Ichikawa, N. Miura, K. Kato, K. Fukuda, Y. Fukuda, "ESD Protection Design in System LSI Using New ESD Modeling for Advanced Devices," 13th RCJ Reliability Symposium, November 4-7, 2003, Tokyo, Japan (URL:

    This paper is available in Japanese only:
    Advanced devices using salicide process technology show poor ESD protection ability. To avoid this, salicide blocking is widely used. However since salicide blocking can cause additional circuit delay, it is important to optimize ESD protection circuits to adequately protect core logic circuits. On the other hand, use of power domain separation methods has been increasing recently to avoid interference between circuits. In this work, we were able to protect against ESD damage between circuit blocks in separated power supplies by using SEQUOIA Mixed Mode simulation. We believe that this kind of simulation methodology is necessary for the design of ESD protection devices for advanced technologies.
    Zipped PDF file
  24. Robert Pack, Valery Axelrad, Andrei Shibkov, Victor Boksha, Judy Huckabay, Rachid Salik, Wolf Staud, Ruoping Wang, Warren Grobman, “Physical & Timing Verification of Subwavelength-Scale Designs using Physical Simulation,” SPIE Microlithography 2003, Santa Clara, USA
    PowerPoint Slides
  25. D. Pramanik, M. Cote, K. Beaudette, V. Axelrad, “Assessing Technology tradeoffs for 65nm logic circuits”, SPIE Microlithography 2003, Santa Clara, USA PowerPoint Slides
  26. V. Axelrad, Y. Huh, J.W. Chen, P. Bendix, "A Novel CDM-like Discharge Effect During Human Body Model (HBM) ESD Stress," SISPAD 2002, Sept. 2002, Kobe, Japan

    Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern integrated circuits. Thinner gate oxides, complex chips with multiple power supplies and/ or mixed-signal blocks, larger chip capacitance and faster circuit operation all contribute to increased ESD-sensitivity of advanced semiconductor products. Detailed understanding of complex circuit-device interactions is essential for the design of effective ESD protection. This paper presents the analysis of a previously unreported ESD phenomenon—a CDM-like (Charged Device Model) discharge between a grounded-gate ESD protection MOSFET and the chip capacitance. The effect has serious implications for the ESD failure threshold and must be considered in the design of robust semiconductor products. An important consequence of the effect is that a circuit-level technique commonly used to reduce the Vdd and Vss power noise coupling—the addition of a decoupling capacitor—can result in strong current spikes and thus degrade ESD performance.

  27. Yoon J. Huh, Valery Axerad, Jau-Wen Chen and Peter Bendix, "The Effects of Substrate Coupling on Triggering Uniformity and ESD Failure Threshold of Fully Silicided NMOS Transistors", VLSI Technology Symposium, June 2002, Honolulu, Hawaii, USA

    We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5microns or bulk wafer is used.

  28. A.Balasinski, L.Karklin, V.Axelrad "Impact of Subwavelength CD Tolerance on Device Performance ", SPIE 4692, 2002, Santa Clara, USA

  29. L. Karklin, S. Mazor, D.Joshi1, A. Balasinski, and V. Axelrad, "Sub-wavelength Lithography: An Impact of Photo Mask Errors on Circuit Performance ", SPIE 4691, 2002, Santa Clara, USA
    PowerPoint Slides
  30. W. Iandolo, O. Ray, A. Balasinski, L. Karklin, V. Axelrad, "Identification of Electrical Signatures of Mask Defects: A Novel Procedure for Mask Disposition," Interface 2001, San Diego, USA

    Semiconductor International writes about this paper: The industry can certainly agree that photomasks are not the commodity items they once were. Simply looking at the price tags of some of the most complex masks in use today will tell you that. With the increasing complexity of resolution enhancement techniques (RETs), and the rising costs that go with it, discussions have turned from mask defects to printable mask defects. After all, it's not cost-effective anymore to trash or even try to repair every mask that has a defect if the error won't even appear on the printed wafer.

    Researchers at Cypress Semiconductor (San Jose), working in conjunction with Numerical Technologies Inc. (San Jose) and Sequoia Design Systems (Woodside, Calif.), have taken this concept a step further. In a paper prepared for Interface 2001 (which was scheduled for November, but was cancelled), they detailed the notion of evaluating the impact of mask defects on device parameters. One aspect of the argument for such measures is that the sizes of legible RET mask features are in the range of minimum detectable defects. Assessing defects by their size and location, therefore, is no longer feasible.

  31. V. Axelrad, Y. Huh, J.W. Chen, P. Bendix, "Investigations of Salicided and Salicide-Blocked MOSFETs for ESD Including ESD Simulation," SISPAD 2001, Athens, Greece

    Standard salicided MOSFETs have been repeatedly shown to have inferior ESD protection properties in comparison to salicide-blocked MOSFETs. Standard explanations typically attribute this to shallower current flow and higher peak current density in salicided devices due to the higher conductivity of salicides. In this work we present a numerical analysis of the phenomenon using physical mixed-mode circuit-device simulation. Our results show that the inherent lack of thickness uniformity known to exist in salicide layers can lead to local concentration of current flow and thus local failure of the device.

  32. A.Balasinski, L.Karklin, and V.Axelrad, "An Integrated Simulation Scheme to Ensure Design Shrinkability for sub-100 Nanometer Technologies," Mixed Design of Integrated Circuits and Systems, MIXDES2001, Zakopane, Poland, June 21-23, 2001

    ABSTRACT : We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation that should meet predefined conditions set forth by the layout control lines called tolerance contours. These contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as ION and IOFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

  33. V. Axelrad, A. Al-Bayati, B. Adibi, "A Simulation Study of CMOS Performance Improvement by LTP versus RTP SDE Profiles," Ion Implantation 2000, Alpbach, Austria

    Laser Thermal Processing (LTP) dramatically changes the feasibility of ultra shallow and highly doped Source-Drain Extensions (SDE). In comparison to conventional Rapid Thermal Processing (RTP) profiles, steeper profiles and higher peak concentrations are achieved. This is of particular importance for sub-100nm devices, where limited steepness of RTP profiles can result in significant source-drain resistance (Rsd) and severe short-channel effects. In this work we demonstrate that LTP technologies can reduce the source/drain resistance Rsd by more than 70% for Lpoly below 100nm in both NMOS and PMOS. This leads to increases in saturation currents by up to 10%. Significant improvements in very deep submicron MOSFET performance can thus be expected as a result of this new technology being deployed.

  34. Sharad Saxena, Patrick D. Mc Namara, Andrei Shibkov, Valery Axelrad and Carlo Guardiani, "Circuit-Device Codesign for High Performance Mixed-Signal Technologies," SISPAD 2000, Sept. 2000, Seattle, WA, USA

    System on Chip designs require low cost integration of analog and digital blocks. Often, the analog requirements are not considered sufficiently early in the device design cycle, resulting in devices that are suboptimal for the analog components. This paper presents an innovative methodology for deriving comprehensive device specifications based upon a set of Figure-of-Merit circuits which account for both analog and digital requirements. By utilizing these specifications for device design, a more efficient codevelopment of mixed-signal processes, libraries and products is possible. The methodology is illustrated with an example based upon an advanced 120nm CMOS technology.

  35. L.Karklin, A.Balasinski, and V.Axelrad, "A Novel Procedure to Evaluate Design Scalability Based on Device Performance Linked to Photolithography", International Microprocesses and Nanotechnology Conference, July 11-13, 2000 Tokyo, Japan
  36. V. Axelrad, N. Cobb*, M. O’Brien*, V. Boksha**, T. Do*, T. Donnelly*, Y. Granik*, E.Sahouria*, A. Balasinski***, "Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs," ISQED 2000, March 20-22, 2000, San Jose, California

    Degradation of lithographic pattern fidelity is a major cause of yield loss in VLSI manufacturing. A general methodology for full-chip analysis and improvement of yield loss due to lithographic effects is proposed. The approach is based on: a) extraction of pattern fidelity statistics using a full-chip layout engine, b) full-chip Optical Proximity Correction (OPC) to improve pattern reproduction, and c) estimation of yield losses due to line variability, using transistor sensitivity to pattern registration obtained from physical transistor modeling. As a result, yield estimates related to either pattern reproduction fidelity or transistor parametric data variations (such as leakage or drive current) are generated. The method is efficient and well suited for application to modern VLSI designs of memory or logic devices.

  37. A. Balasinski, H. Gangala, V. Axelrad* and V. Boksha**, Cypress Semiconductor, San Jose, CA and *Sequoia Design Systems, Woodside, CA and **MIT, Cambridge, MA, "A Novel Approach to Simulate the Effect of Optical Proximity on MOSFET Parametric Yield," IEDM 1999, Washington, D.C., Dec. 5-8, 1999

    The effect of mask and photolithography process variations on MOSFET performance and parametric yield is studied. Dense layout of 0.16 µm six-transistor SRAM cell was used to first verify the accuracy of optical proximity (OPC) and mask simulations. This was followed by extraction of channel length dependent MOSFET drive current for the different OPC serif and misalignment options within the latitudes of mask generation and photolithography processes. Finally, yield was simulated based on statistical distributions of  MOSFET parameters.

  38. V. Axelrad, M. Duane, "Controlling Mesh Effects in Integrated Process and Device Simulation," 3rd International Workshop on Statistical Metrology, Hawaii, USA, June 98

    Using a well-constructed mesh is crucial to obtain good results in TCAD. The paper demonstrates that the conventional approach - using the process simulator mesh in device simulation - can lead to dangerous inaccuracies in the solution. The example shows oscillations in Idlin as a function of Tox if a process simulator mesh is used. An automatically generated optimized mesh is shown to solve the problem.

  39. V. Axelrad, "Grid Quality and Its Influence on Accuracy and Convergence in Device Simulation," IEEE Trans. on CAD, Vol. 17, Number 2, Feb. 1998

    A discussion of the relationship between mesh quality and stability of simulation.

  40. V. Axelrad, J. Kibarian, "Statistical Aspects of Modern IC Designs", ESSDERC 97, Stuttgart, Germany, Sept. 1997

    Review paper discussing the interface between process and circuit design.

  41. V. Axelrad, G. Long, P. Kuepper, "Elimination of Meshing Noise in Statistical TCAD," 2nd International Workshop on Statistical Metrology, Kyoto, Japan, June 1997

    Demonstrates the importance of using a well-constructed boundary conforming mesh to obtain meaningful statistical results from coupled process-device simulation.
  42. V. Axelrad, "Fast and Accurate Aerial Imaging Simulation for Layout Printability Optimization" SISPAD 1995

    Discusses the application of highly efficient algorithms based on the Fast Fourier Transform (FFT) to achieve fast and accurate aerial image calculation.
  43. V. Axelrad, R. Klein, "Electrothermal Simulation of an IGBT", International Symposium on Power Semiconductor Devices & ICs, Tokyo, Japan, 1992.

    Studies the effect of self-heating on the snap-back characteristics of an IGBT device.